On the Formal Semantics of a CHDL - A Case Study
نویسنده
چکیده
The semantics of HDL descriptions influences all facets of VLSI design such as synthesis, test, verification, logic simulation and fault simulation. In this paper formal semantics of the intermediate language TREEMOLA, used in the MIMOLA hardware design system MSS, is presented. In particular semantics of module declarations, described at the Register Transfer Level by the CHDL MIMOLA, is defined.
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